Minimizing EMI from Via Transitions in Multilayer PCBs - Part 2
Via transitions are among the most important EMI-control points in a multilayer PCB. Whenever a high-speed signal moves from one layer to another, the signal current and its return current must move through a three-dimensional structure containing vias, pads, antipads, reference planes, and dielectric material. The most important design principle is simple: keep the signal current and return current close together through the entire transition. A smaller current loop produces lower inductance, less field leakage, and lower EMI.
PCB DESIGNPCB MANUFACTURING
Atanu
9/4/20262 min read
Minimizing EMI from Via Transitions in Multilayer PCBs - Part 2
Via transitions are one of the most common EMI risk points in a high-speed multilayer PCB. When a signal moves from one layer to another, its return current must also transition through the reference-plane system.
If that return path is interrupted, current detours through a larger loop. The resulting increase in loop area and inductance can produce crosstalk, ground bounce, ringing, timing errors, and radiated emissions.
The via itself is only part of the problem. The complete transition includes:
Signal barrel.
Pads.
Antipads.
Reference planes.
Via stubs.
Return vias.
Dielectric material.
Nearby signal structures.
Return vias are the first line of defence
For an important single-ended transition, place 2–4 ground return vias close to the signal via. Keep the arrangement symmetrical and connect the return vias to all relevant ground planes.
A practical starting distance is 50–100 mils, although higher-frequency structures often require much tighter placement.
Return vias reduce EMI by providing a short, low-inductance path for the return current. They also help form a quasi-coaxial structure around the signal via.
For shielding, a useful initial rule is:
p ≤ λ_eff / 20
where p is via-fence pitch and λ_eff is the guided wavelength at the highest significant frequency.
The final spacing must also consider via diameter, pad size, registration, fabrication limits, and resonance of the complete via array.
Stitching capacitors for plane changes
If a signal changes from a ground reference to a power reference, ground vias alone may not provide a valid high-frequency path between the planes.
A stitching capacitor can provide the required AC connection. A common starting value is:
C_stitch = 0.1 µF
Place the capacitor close to the signal transition and use short connections with nearby power and ground vias.
At high frequency, mounting inductance is critical:
Z_total ≈ j × ω × L_mount + 1 / (j × ω × C)
A compact capacitor with a very short mounting loop can outperform a larger capacitor connected with long traces.
Eliminate via stubs
Unused through-hole via sections can behave as quarter-wave resonators:
l_stub ≈ λ_eff / 4
Long stubs can cause insertion-loss notches, ringing, and radiated EMI. Backdrilling removes the unused barrel and is especially valuable for thick boards and high-speed serial links.
Blind, buried, and microvias can also reduce via length and eliminate surface stubs, but they require more complex fabrication processes.
Design the stackup first
The stackup should place every critical signal layer close to a continuous reference plane. Prefer ground as the local reference for high-speed channels and avoid routing over plane splits.
Central ground-plane structures can improve field containment and reduce the number of reference-plane changes.
Validate the complete structure
Analyse critical transitions with a three-dimensional electromagnetic solver. Include the actual pads, antipads, barrels, return vias, reference planes, dielectric thickness, and nearby structures.
Review:
S-parameters.
Insertion loss.
Return loss.
TDR impedance.
E-field and H-field distribution.
Differential-to-common-mode conversion.
Near-field radiation.
The main principle is straightforward: keep the signal current and return current close together through the entire transition.
A carefully designed via transition reduces loop area, controls impedance, limits field leakage, and improves both signal integrity and EMC performance.
